培训方式以讲课和实验穿插进行

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课程介绍：

????此课程展现了Incisive设计和验证平台的从行为级，RTL级到门级的完整的设计验证流程，本课程主要是针对具有集成电路设计和验证基本知识的设计或验证工程师而准备。通过本课程的培训使用户对Cadence的验证方法和工具使用有一个全面、整体概念，用户在实际工作中能根据所掌握的概念和方法，应用先进的验证方法提高集成电路的验证效率和质量。

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Incisive??设计验证平台介绍：

????要获得今天的复杂集成电路功能验证所需的速度和效率要求我们采用一体化的验证方法。Cadence Incisive平台适用于从系统设计到系统内设计的所有设计验证领域 – 嵌入式软件、控制、数据通路、模拟/数字混合信号。

Incisive平台是世界上首个单内核验证平台，Incisive单内核架构支持Verilog, VHDL, SystemVerilog, SystemC, SCV(SystemC Verification), PSL/Sugar,算法开发和模拟/数字混合信号验证。它采用了通用的用户界面和调试环境，支持全事务级的验证，一体化测试方法，按需加速。Incisive平台提供业界快速，高效的验证方法。

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课程目标：

After completing this course, you should be able to:

■?Briefly describe Incisive simulation

■?Set up your environment for Incisive simulation

■?Compile, elaborate, and simulate your design and testbench

■?Debug your design with the textual and graphical interfaces

■?Incorporate components of “foreign” languages in your simulation

■?Annotate SDF timing data to the HDL portions of your design

■?Incorporate C and C++ applications into your simulation

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课程安排：

Unit 1

Time Topic

09:30-09:45??Introduction & agenda

09:45-10:00??Incisive simulation overview

10:00-10:30??Setting up the simulation environment

10:30-12:00??Compiling your design

12:00-13:30??LUNCH

13:30-02:15??Elaborating your design

02:15-03:45??Simulating your design

03:45-05:00??Debugging with the textual interface

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Unit 2

Time Topic

09:30-10:00??Debugging with the textual interface

10:00-11:15??Debugging with the graphical interface

11:15-12:45??Simulating mixed-language designs

12:45-01:45??LUNCH

01:45-02:00??Introducing simulator utilities

02:00-03:30??[optional] Annotating SDF timing

03:30-05:00??[optional] Linking user applications